The invention relates generally to a method for fabricating a semiconductor device and, more specifically, to a technology of forming a cell transistor on a partial-insulated (PI) substrate.
In a system comprising a plurality of semiconductor devices, a semiconductor memory apparatus is configured to store data generated or processed therein. For example, if a request from a data processor such as a central processing unit (CPU) is received, the semiconductor memory apparatus outputs data to the data processor from unit cells therein or stores data processed by the data processor to the unit cells, according to an address transmitted with the request.
As data storage capacity of semiconductor memory apparatus has increased, sizes of semiconductor memory apparatus have not increased proportionally. Thus, various elements and components used for read or write operations in the semiconductor memory apparatus have also reduced in size. Accordingly, components and elements unnecessarily duplicated in the semiconductor memory apparatus, such as transistors or wires, are combined or merged to reduce the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory apparatus affects improvement of integration.
Due to the high degree of integration of semiconductor devices, the size of, for example, a field effect transistor (FET) that includes bulk silicon as the body is smaller; problems such as a short channel effect and increase of leakage current as well known by a person having an ordinary skill in the art are occurred.
In order to prevent the short channel effect and increase of leakage current, a method for fabricating a semiconductor device to form a transistor over a substrate having a silicon on insulator (SOI) structure has been suggested. The SOI substrate includes an insulating film formed over a lower semiconductor substrate and a silicon film formed over the insulating film. When a floating body transistor is formed in the SOI substrate, a body of the transistor is formed in the silicon film formed over the insulating film. The body of the neighboring transistor is isolated by a device isolation film that is contacted to the insulating film in order to reduce the leakage current. Source and drain regions are formed using both sides of the three-dimensional transistor body, thereby increasing the channel length rather than a conventional two-dimensional plane structure.
However, when the transistor is formed over the SOI substrate, a floating body effect is generated. The SOI substrate includes an insulating film positioned between the semiconductor substrate and the silicon film. The SOI substrate has a capacitor structure. When charges move repeatedly through the body of the transistor, the charges are accumulated in the capacitor through generation and recombination of a bias and a carrier, thereby degrading the operation of the semiconductor device. The threshold voltage of the transistor fluctuates due to the charges accumulated in the capacitor. The capacitor repeatedly accumulates and emits the charges, thereby generating thermal energy. The generation of leakage current resulting from a field effect concentration is called a Kink effect.
In order to prevent degradation of the operation characteristic of the semiconductor device due to the structural characteristic of the SOI substrate, a partial-insulated (PI) substrate has been suggested. In the PI substrate, a portion of the silicon film is connected to the semiconductor substrate included in the bottom portion of the SOI substrate and the upper portion of the insulating film, thereby partially insulating the upper portion and the lower portion in the SOI substrate. Hereinafter, a method for fabricating a semiconductor device in the PI substrate is described.
FIGS. 1a and 1b are plane diagrams illustrating a mask structure for fabricating a general semiconductor memory apparatus. Specifically, FIG. 1a shows an ISO mask 102, a substrate connecting mask 104, a fin mask 106, and a gate mask 108 for manufacturing a unit cell of 8 F2 including a fin transistor. FIG. 1b shows an ISO mask 112, a substrate connecting mask 114, a fin mask 116 and a gate mask 118 for manufacturing a unit cell of 6 F2.
Hereinafter, a method for forming a fin transistor over a PI substrate with the mask shown in FIG. 1a or 1b is described.
FIGS. 2a to 2h are perspective diagrams illustrating a method for fabricating a general semiconductor device using a mask pattern shown in FIG. 1a. 
Referring to FIG. 2a, a sacrificial film 204 is formed over a semiconductor (e.g., Si or SiGe) substrate 202. A first silicon film 206 is formed over the sacrificial film 204, and a first hard mask film (not shown) is formed over the first silicon film 206. The sacrificial film 204 has a different wet etching selectivity than those of the semiconductor substrate 202 and the first silicon film 206. After the first photoresist film (not shown) is coated over a first hard mask film, the photoresist film is patterned using the substrate connecting mask 104 shown in FIG. 1a. The first hard mask film is etched using a second photoresist film, and the first silicon film 206 and the sacrificial film 204 are etched as shown in FIG. 2b. The first hard mask film is removed.
Referring to FIG. 2c, a second silicon film 208 is formed over the structure including the first silicon film 206 and the sacrificial film 204, thereby obtaining a PI substrate.
Referring to FIG. 2d, after a second hard mask film 210 is formed over the PI substrate, a Shallow Trench Isolation (STI) process is performed to form a trench by an etching process using an ISO mask that defines an active region. As shown in FIG. 2e, the exposed sacrificial film 204 is selectively wet-etched. For example, when the sacrificial film 204 includes SixGe1−x where x is 0.8, i.e. Si0.8Ge0.2, the sacrificial film 204 except for the semiconductor substrate 202, the first silicon film 206, and the second silicon film 208 is selectively wet-etched using a mixture solution having a composition ratio of HNO3(70%):HF(49%):CH3COOH(99.9%):H2O=40:1:2:57 which is diluted in H2O to a proper concentration.
Referring to FIG. 2f, a vacant space formed by the STI process is filled with an isolation insulating film 212. The isolation insulating film 212 is planarized through a chemical mechanical polishing (CMP) process to expose the second hard mask film 210. Through the wet-etching process, the isolation insulating film 212 is etched at a given depth to adjust the height, and the second hard mask film 210 is removed, thereby exposing the top portion of the second silicon film 208 defined as an active region. In order to form a fin region, a third hard mask film (not shown) is deposited over the resulting structure including the top portion of the second silicon film 208. A second photoresist film (not shown) is coated over the third hard mask film (not shown). Thereafter, the second photoresist film is removed from a fin-expected region of the transistor using the fin mask 106. The third hard mask film and the isolation insulating film 212 are removed, thereby forming a trench 209 to form a fin channel region. After the fin channel region is formed through the above-described process, the second photoresist film and the third hard mask film are removed.
Referring to FIG. 2g, a gate insulating film (not shown) is formed over the first and second silicon films 206 and 208, the semiconductor substrate 202. A gate lower electrode 216 and a gate upper electrode 218 are formed over the structure including the gate insulating film. The trench 209 is filled by the gate lower electrode 216. A gate hard mask film 220 is deposited over the gate upper electrode 218.
After a third photoresist film (not shown) is coated over the gate hard mask film 220, the third photoresist film is patterned with a gate mask. As shown in FIG. 2h, the gate hard mask film 220, the gate upper electrode 218, and the gate lower electrode 216 are sequentially etched with the third photoresist film. After the gate pattern is completed, the third photoresist film is removed.
Using a similar process as manufacturing a unit cell of a DRAM, an LDD region of the cell transistor is formed, and a sidewall insulating film is formed at sidewalls of the gate pattern. Thereafter, the process for manufacturing a unit cell of a DRAM including a fin transistor is completed through a process for forming a cell transistor that includes forming a cell contact plug, forming a bit line contact and a bit line, forming a capacitor contact and a capacitor and forming a metal line.
FIG. 3 is a perspective diagram illustrating a problem of the semiconductor device shown in FIGS. 2a to 2h. Specifically, FIG. 3 shows a cross-section of the perspective diagram shown in FIG. 2f. 
In a cross-section of the fin region after the isolation insulating film 212 is formed, a partial region between the first and second silicon films 206 and 208 is insulated from the semiconductor substrate 202 by the isolation insulating film 212. In the PI substrate, after the second silicon film 208 is formed, the sacrificial film 204 and the residual sacrificial film 204 except for the etched portion of the first silicon film 206 are selectively removed by a wet-etching process using the substrate connecting mask defined with the same width as that of the fin mask as shown in FIG. 2b, and then the isolation insulating film is filled. By using the fin mask defined with the same width as that of the substrate connecting mask in FIG. 2f, a fin region is formed only in the region which is not insulated between the semiconductor substrate 202 and the first and second silicon films 206, 208. As a result, the width of the fin region is substantially the same as that of the substrate connecting portion of the PI substrate.
When a misalignment occurs between the substrate connecting mask and the fin mask in the above-described fin cell transistor, the connected fin region and the silicon substrate of the fin channel do not correctly match each other. The fin region may be formed partially to be leaning toward the partial insulating region. In a general DRAM structure, a contact region connected to a bit line is located between two cell transistors formed over one active region, and a contact region connected to a storage node is positioned at both sides of the two cell transistors. If a misalignment occurs when the fin cell transistor is applied to cell structure of the DRAM, the two fin cell transistors formed over one active region cannot be formed to be symmetrical. As a result, operation characteristics between the source/drain of the two fin cell transistors are differentiated, so that characteristics of the cell transistors connected to both sides of one bit line are also changed.
When a fin transistor is formed over the PI substrate by the same method in a conventional method, a partial insulating region is formed in the bottom portion of the region connected to the bit line between the two neighboring fin transistors, and a partial insulating region is not formed in the bottom portion of the fin region of the fin transistor. As a result, there is a limit to decrease the short channel effect because the size of the partial insulating region is the same as the width of the active region in one side, and same as the length of the source/drain regions in the other side.